PORTFOLIO / FPGA TRAFFIC CONTROLLER

FPGA Traffic Light Controller

A synthesizable VHDL/Verilog-based traffic light controller with adaptive timing, deployed on an FPGA dev board.

◆ FPGA TRAFFIC CONTROLLER
INTERSECTIONS
1
STATE TRANSITIONS
8
CLOCK FREQUENCY
50MHz

Project Overview

A digital logic design project built entirely in VHDL and simulated/synthesized for a low-cost FPGA board — implementing a finite-state-machine-driven traffic light controller with pedestrian crossing and adaptive timing based on IR vehicle sensors.

Specifications & Circuit Type

Design Language

VHDL, with a Verilog testbench for cross-verification

Target Hardware

Xilinx Artix-7 based FPGA development board

Logic Design

Finite State Machine (FSM) with 8 traffic states

Circuit Type

Fully digital synchronous logic clocked at 50MHz, with debounced IR sensor inputs

Inputs

IR vehicle sensors on each approach, pedestrian call button

Verification

Full testbench simulation before on-board synthesis

Technologies Used

VHDL Verilog FPGA FSM Design Xilinx Artix-7 Digital Logic Testbenches

Key Features

✓ FSM-driven traffic sequencing
✓ Adaptive timing via IR vehicle sensors
✓ Pedestrian crossing request logic
✓ Fully simulated before synthesis
✓ Synthesizable, resource-efficient RTL
✓ Expandable to multi-intersection sync

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